Course 090 Plasma Etching for Microelectronics Applications: From Fundamental to Practical Applications

Dr. Maxime Darnon, LN2/CNRS, Sherbrooke, Canada, is teaching this E-course in Plasma Etching for Microelectronics Applications. From Fundamental to Practical Applications. This is an E-Course in mixed format. Combining self-paced e-learning with live weekly sessions with the instructor. Duration in total is four weeks of effective learning. Content based on complete agenda of the public course #088. The below dates are fixed. This course is intended to provide an understanding of plasma processes for CMOS applications and ULSI technology. You will learn the fundamental and practical aspects of front end and back end plasma processes for deep submicron CMOS logic processes. The course is based on experimental results obtained using commercial etchers connected to very powerful diagnostics of the plasma and the plasma surface interaction. The discussions cover several aspects of etch processes of materials integrated in advanced CMOS devices, etch mechanisms, and situations that may be encountered for some important plasma processes. Option 2: Take the short E-course #089 Plasma Etching for Microelectronics Applications. Combining self-paced e-learning with live weekly sessions with the instructor. Duration in total is two weeks of effective learning. Content based on the first two days of the public course #088. Option 3: Travel and join the 4-day public live course in classroom at selected venue in Europe. View link for #088 Plasma Etching for CMOS Technology and ULSI Applications

Available course dates

This course has no planned course dates.

If you are interested in this course, contact us at cei@cei.se

TECHNOLOGY FOCUS

Extensive efforts to miniaturize semiconductor devices is largely attributed to lithography and etching technologies that allow semiconductor thin films patterning in the range of dimensions determined by the semiconductor road map.

During more than 30 years, classical materials, such as aluminum, SiO2, and polysilicon, have been integrated in semiconductor devices.
Nowadays, the technology imposes to work with new materials at each technological node. The integration of new high k and low k dielectric materials, metals at the front and back end of device fabrication, bring on new problem categories.

This imposes the necessity to quickly build up expertise at a rate unprecedented in all the history of semiconductor manufacturing.

Instructor

Dr. Maxime Darnon

COURSE CONTENT

This course is intended to provide an understanding of plasma processes for CMOS applications and ULSI technology. We will discuss fundamental and practical aspects of front end and back end plasma processes for deep submicron CMOS logic processes.


The course is based on experimental results obtained using commercial etchers connected to very powerful diagnostics of the plasma and the plasma surface interaction. The discussions cover several aspects of etch processes of materials integrated in advanced CMOS devices, etch mechanisms, and situations that may be encountered for some important plasma processes.

Fundamental parameters obtained from advanced characterizations are used to discuss and analyze plasma etch processes. The emphasis is on real problems, fundamental understanding of processes used in manufacturing, considerations for integration with other steps, and issues brought by the fast device scaling.

Processes covered in detail include silicon gate patterning and all the problems related to critical dimension control as well as results on metal gate and high k dielectric etching. The etch processes associated with the integration of low k materials will be extensively discussed.

WHO SHOULD ATTEND

Any person with a technical background wishing to obtain a better understanding of the mechanistic aspects of plasma-assisted etching, or of reactive gas plasma-surface interactions in general, should benefit from taking this course.

Although the emphasis of the course is on the ULSI circuit fabrication applications, much of the information presented should be of value in the implementation of other processes involving reactive gas plasmas.

A familiarity with the basic concepts of plasma-assisted etching would be helpful but is not essential as the course includes a short summary of the basics.

Day One

Plasma Fundamentals

  • Fundamentals of Cold Plasma Physics
  • Plasma Sources used for Etching Application
  • Plasma Surface Interactions Involved in Etching

Day Two

Etching Fundamentals

  • Pattern Transfer in Plasma Etching
  • Profile Control for Plasma Etching
  • Monitoring and Controlling a Plasma Etching Processes
Day Three

Plasma Etching for Front End Of Line application

  • Photoresist and Mask
  • Poly Silicon Gate Etching
  • Metal Gate / High-k Etching
  • Atomic Layer Etching
  • New Patterning Technologies
  • New Transistor Architectures

Day Four

Plasma Etching for Back End Of Line Application

  • Etching with a Fluorocarbon-Based Plasma
  • Spacers Etching
  • Contacts Etching
  • Dense SiOCH Etching for Interconnects
  • Porous SiOCH Etching for Interconnects
  • High Aspect Ratio Structures Etching

Day 1

Power Amplifier Basics and Signal Environments

Linear amplifier modes are described with quantitative analysis of power, efficiency and linearity tradeoffs in uncompensated form leading into a discussion of the device technologies currently available for PA design, including LDMOS, GaAs MESFET and HBT, SiC and GaN. Differences between bipolar and FET devices, and the effects of different kinds of parasitic effects will be discussed using circuit analysis and CAD models. Possibilities for tailoring the characteristics of devices for optimum efficiency and linearity will be presented. Particular emphasis is given to correct fundamental and harmonic matching. The impact of non-ideal harmonic terminations in practical Class AB designs will be analysed quantitatively. Various modulation systems (QPSK, EDGE, CDMA, OFDM) will be reviewed from the viewpoint of PA requirements. 

  • Introduction
  • Classical PA Modes, Class A, Class AB, Class B, Class C
  • PA Device Technology
  • Optimum Device Characteristics for Class AB Operation
  • Modulation Systems in Wireless Communications QPSK, GSM, EDGE, OFDM
  • Effect of Signal Environment on RFPA Design

Day 2

Class AB PA Design

We will focus on practical issues in the design and manufacture of PAs for RF and MW Systems. Several design examples will be demonstrated, including a GaAs MESFET, a GaAs HBT, and a high power LDMOS device.

  • Class AB circuits
  • Harmonic Terminations
  • CAD Design Examples

Day 3

Power Amplifier Non-Linearity and Signal Environments

We will focus on the non-linear properties of RF PAs, their source, manifestation, and methods for their characterization and modeling. A topical issue of great impact in modern linearised multi-carrier PA (MCPA) applications is memory effects.This subject will be illustrated with device measurements, and physical causes and remedies will be discussed.

There will be a full treatment of bias network design.The process of converting a measured PA gain compression and AM-PM characteristic into spectral and EVM distortion, and the issues involved, will be discussed using several different modulation environments, including GSM-EDGE and WCDMA.

  • Non-Linear PA Characteristics, Gain Compression, AM-PM
  • Physical Origins of AM-PM, Analysis
  • Peak to Average Power Ratio Issues in Modern Signal Environments
  • Spectral Regrowth and EVM
  • Power Series, Volterra Series. Model Fitting using Measured Data
  • Envelope Simulation using EDGE, OFDM signals
  • Memory Effects, Definition, Dynamic Gain/Phase Measurements, Causes and Remedies
  • Bias Network Design and Stability

Day 4

Efficiency Enhancement Techniques

We will focus on the key issue of power back-off (PBO) efficiency, and LINC (linear amplification using non-linear components). Envelope management methods and tracking techniques in PA design will be presented. These include classical techniques such as the Chireix out-phasing method, the Khan and the Polar Loop envelope reconstruction approaches and the Doherty PA. Other less well-known techniques will be discussed, with emphasis on the broader band requirements, which future WiMax systems will require. Ultra high efficiency amplifier modes, Classes C, D, E, and F will be analyzed as possible candidates for LINC implementation and as stand-alone possibilities in systems using digital pre-distortion or feed forward linearization. Finally, PA architecture, including multistage effects, power combining techniques, and load pull design will be discussed. Step-by-step examples of two MMIC PA designs, one with modest, and a further example with wideband operation will be given – this will include technology evaluation to packaging considerations.

  • Power Combining Techniques
  • Balanced and Push-Pull Operation
  • Load-Pull Techniques
  • Microwave PA Design – including step-by-step MMIC PA design examples

Day 5

An introduction to mm-wave components and applications

mm-wave circuits are becoming more commonplace as semiconductor technologies mature which provide performance up to 100 GHz and beyond. This Session will offer an introduction to the technologies and components operating at mm-wave and some of the key applications. Amplifier design at mm-wave will be discussed with a design example. Differences in the approach of amplifier design at mm-wave compared to lower frequency will be highlighted. In addition, an introduction will be given for other common component types at mm-wave: mixers, multipliers, oscillators and mixed (analogue/digital) signal techniques. Packaging, interconnection and combining will also be considered. Finally, the emerging field of sub-mm-wave (Terahertz) components will be introduced.

  • Applications in mm-wave
  • mm-wave technologies
  • Amplifiers – including a design example
  • Common mm-wave components
  • Packaging at mm-wave
  • Terahertz 

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